1. Field of the Invention
The present invention relates to a test circuit device and a semiconductor integrated circuit device for testing a semiconductor memory device and more particularly, to a test circuit device and a semiconductor integrated circuit device for identifying an error in stored data at a memory cell level.
2. Description of the Background Art
In a memory cell of a DRAM (Dynamic Random Access Memory), data is held in a charge form in a capacitor. In the case of reading data from a memory cell which simply accumulate charges in a capacitor and therefore could not drive a signal line (bit line), with a pair of complementary data lines used as data lines for receiving memory cell data, a small potential difference between the complementary data lines of the pair is amplified to enable read out the memory cell data.
FIG. 33 is a diagram schematically showing the configuration of a main portion of a conventional DRAM. In FIG. 33, a pair of bit lines BL and ZBL and two word lines WL0 and WL1 are shown. A memory cell MC0 is disposed at a crossing between bit line BL and word line WL0, and a memory cell MC1 is disposed at a crossing between bit line ZBL and word line WL1.
Each of memory cells MC0 and MC1 includes a capacitor MQ for storing data and an access transistor MT for coupling a corresponding capacitor MQ to an associated bit line BL or ZBL in accordance with a signal potential on a corresponding word line WL (WL0 or WL1). Access transistor MT is formed of an N-channel MOS transistor (insulated gate field effect transistor).
Corresponding to the pair of bit lines BL and ZBL, a sense amplifier SA is disposed. When activated, sense amplifier SA amplifies the potential difference between bit lines BL and ZBL to drive bit lines BL and ZBL to the H level (for example, power supply voltage level) and the L level (for example, ground voltage level) in accordance with data stored in a selected memory cell.
Bit lines BL and ZBL are coupled to internal data lines IO and ZIO via a column selection gate YG. Column selection gate YG includes transfer gates TX, which are made conductive in response to a column selection signal CSL to couple bit line BL to internal data line 10, and complementary bit line ZBL to complementary internal data line ZIO. Connection between bit lines BL and ZBL and internal data lines IO and ZIO is uniquely determined irrespective of the position of a selected memory cell.
Internal data lines IO and ZIO are coupled to a write/read circuit RWK, which in turn is coupled to an input/output circuit IOK for inputting/outputting data externally.
In the configuration illustrated in FIG. 33, one word line is driven to a selected state, and data stored in a memory cell is read onto one of bit lines BL and ZBL. For example, when word line WL0 is selected, the data stored in memory capacitor MQ of memory cell MC0 is transmitted to bit line BL. Complementary bit line ZBL maintains a precharge state. Sense amplifier SA amplifies the potential difference between bit lines BL and ZBL. Consequently, even if a small potential change is caused on bit line BL in accordance with the charges stored in memory capacitor MQ, by amplifying the potential difference between bit lines BL and ZBL, the data in the memory cell can be read with reliability.
Where word line WL1 is selected, the charges stored in capacitor MQ in memory cell MC1 are transmitted to bit line ZBL, and bit line BL maintains the precharge voltage level.
Therefore, when a memory cell is selected, data stored in the memory cell is transmitted to one of bit lines BL and ZBL, and the other bit line maintains the precharge voltage level and is used as a reference bit line supplying a reference potential at the time of the differential amplification. By using complementary bit lines BL and ZBL, even if the data is stored in a charge form in capacitor MQ in memory cell MC (MC0 or MC1), data can be accurately read.
Write/read circuit RWK includes a write circuit which is activated in writing data to generate complementary write data onto internal data lines IO and ZIO, and a preamplifier (read circuit) which is activated in reading data to amplify complementary internal data on internal data lines IO and ZIO and transmit the amplified data to input/output circuit IOK.
In writing data, input/output circuit IOK generates internal data in accordance with external data DQ and supplies the generated internal data to write/read circuit RWK. In reading data, input/output circuit IOK buffers internal read data supplied from write/read circuit RWK to generate external output data DQ.
In selecting a column, column selection gate YG couples bit lines BL and ZBL to internal data lines IO and ZIO, respectively, in accordance with a column selection signal CSL. The connection between bit lines BL and ZBL and internal data lines IO and ZIO is uniquely determined. There is consequently such a case that the logic level of external write data and that of data actually stored in a memory cell are different from each other depending on the position of the memory cell.
FIG. 34 is a diagram showing an example of data stored in a memory cell in writing data. It is now assumed that, as shown in FIG. 34, in writing data, write/read circuit RWK generates complementary data D and ZD in accordance with internal write data D from input/output circuit RWK and transmits complementary data D and ZD to internal data lines IO and ZIO, respectively, and internal write data D and ZD are at the H and L levels, respectively. When bit lines BL and ZBL are connected to internal data lines IO and ZIO, respectively, in response to column selection signal CSL, data D at the H level is transmitted to bit line BL, and complementary write data ZD on complementary internal data line ZIO is transmitted to complementary bit line ZBL.
Consequently, when word line WL0 is selected, H-level data corresponding to external write data is written into and stored in memory cell MC0. On the other hand, when word line WL1 is selected and memory cell MC1 is selected, complementary write data ZD is written into and stored in memory cell MC1.
That is, data at the same logic level as that of external write data D is stored in the memory cell connected to bit line BL, while complementary write data ZD at the logic level opposite to that of external write data D is stored in the memory cell connected to complementary bit line ZBL.
FIG. 35 is a diagram showing read data in reading data stored in a memory cell. It is now assumed that, in FIG. 35, H-level data is stored in memory cell MC0 and L-level data is stored in memory cell MC1.
When memory cell MC0 is selected, H-level data is read onto bit line BL. A potential difference caused between bit lines BL and ZBL is amplified by sense amplifier SA, bit line BL is driven to, for example, the power supply voltage level, and bit line ZBL is driven to, for example, the ground voltage level. Internal read data RQ and ZRQ on bit lines BL and ZBL are at the H level and the L level, respectively.
When column selection gate YG is made conductive in response to column selection signal CSL, internal read data RQ on bit line BL is transmitted to internal data line IO, and internal read data ZRQ is transmitted to internal data line ZIO. In reading data, write/read circuit RWK generates internal read data RQ in accordance with data RQ and ZRQ on internal data lines IO and ZIO. That is, in reading data, write/read circuit RWK generates internal read data RQ at the same logic level as that of read data RQ on internal data line IO. When input/output circuit IOK generates external output data DQ in accordance with internal read data RQ transmitted from write/read circuit RWK, external output data DQ at the H level the same in level as the H-level data stored in memory cell MC0 is generated.
On the other hand, when memory cell MC1 is selected, the L-level data is transmitted to complementary bit line ZBL. Sense amplifier SA amplifies a potential difference between complementary bit lines BL and ZBL, bit line BL attains the H level, and bit line ZBL attains the L level. Therefore, in this case as well, read data RQ on bit line BL attains the H level, and data ZRQ on complementary bit line ZBL attains the L level. In a manner similar to the case of reading the data stored in memory cell MC0, H-level output data DQ is transmitted externally.
Therefore, when memory cell MC0 is selected, data at the same logic level as that of the data stored in memory cell MC0 is output externally. On the other hand, when memory cell MC1 is selected, external output data having the logic level opposite to that of the data stored in memory cell MC1 is generated.
With such an arrangement that a complementary bit line pair is used, a memory cell is disposed at a crossing between one bit line of the bit line pair and a word line, the sensing or differential amplification operation is performed by sense amplifier SA on the bit line pair with the other non-selected bit line (bit line different from the bit line connecting to the selected memory cell) used as a reference bit line, external read data according to the external write data can be accurately generated.
In the DRAM as described above, when viewed from an outside, the logic level of write data and that of read data are the same irrespective of the position of a selected memory cell, and no problem occurs in practical use. Therefore, for example, in a test, data is written into a memory cell, the data is read from the memory cell, and determination is made on whether or not the read data and written data (expected value data) coincide with each other. Whether the memory cell stores data accurately or not can be determined reliably. By such a function test, for example, a defective memory cell can be detected and repaired through replacement with a redundancy cell.
However, in a test, there is such a case that it is important to analyze transition of stored data at the memory cell level. For example, by detecting whether a failure related to refreshing operation is an xe2x80x9cHLxe2x80x9d failure that data stored in a memory cell changes from the H level to the L level or an xe2x80x9cLHxe2x80x9d failure that data stored in a memory cell changes from the L-level data to the H-level data, a current leak path can be detected. Specifically, if such failures occur due to short circuiting or the like and the HL failure or LH failure at the memory cell level can be detected, the leak path can be identified to be either a leak path connected to the power supply voltage source or a leak path connected to the ground voltage source, and whether the position of the leak is a shorting within the memory cell or a shorting in the bit line can be also detected.
Upon occurrence of a soft error, since such a soft error is caused by an impact ionization phenomenon in a substrate area, although the soft error is not reproducible, only a failure that data stored in a memory cell changes from the H level to the L level occurs. Therefore, even in the case of a soft error which occurs in another test, there is the possibility that such a soft error is specified by detecting the HL failure at the memory cell level.
However, in order to analyze a memory cell failure that a selective change in data (data scramble) occurs at the memory cell level, the analysis has to be made while sufficiently grasping the scrambling of memory cell data due to physical arrangement of a memory array and a test pattern. It is necessary to identify whether the physical position of a memory cell on the memory array depending on a selected word line is connected to the bit line or to complementary bit line for all the memory cells. When the number of memory cells becomes great, the identifying work becomes enormous, and it causes a problem that a failure at the memory cell level cannot be easily analyzed.
As for a self test (BIST; Built In Self Test) in which an on-chip circuit is employed to test a semiconductor memory device for enhancing the testability, since the scale of a test program is small, although whether the memory cell is good or not can be determined, transition of the data at the memory cell level cannot be detected. In addition, a test sequence under execution cannot be monitored externally, so that the correspondence relationship between write test data (test pattern) and a selected memory cell cannot be determined when a failure occurs, which makes analysis of the cause of the failure more difficult.
An object of the present invention is to provide a test circuit device and a semiconductor integrated circuit device capable of easily specifying a failure at a memory cell level.
Another object of the invention is to provide a test circuit device and a semiconductor integrated circuit device capable of easily determining transition of stored data at a memory cell level.
Further object of the invention is to provide a test circuit device and a semiconductor integrated circuit device capable of easily analyzing a failure.
A test circuit device according to a first aspect of the invention includes: an expected value data register for storing test expected value data indicative of an expected value of test data read from a selected address in a memory array having a plurality of memory cells; a mode determining circuit for determining a possibility of occurrence of a failure designated by a failure mode instruction signal in data stored in a memory cell of the selected address in accordance with the selected address, the test expected value data and the failure mode instruction signal; and a failure determining circuit for determining whether or not a failure occurs in the data stored in the memory cell of the selected address on the basis of an output signal of the mode determining circuit, the test expected value data, and test data from the selected address, and outputting a signal indicative of a result of the determination.
A semiconductor integrated circuit device according to a second aspect of the invention includes: a memory array having a plurality of memory cells arranged in rows and columns; a reading circuit for generating internal read data in accordance with data of a selected memory cell in the memory array; a register for storing test expected value data indicative of an expected value of the internal read data; a determining circuit for determining whether the internal read data coincides with the test expected value data or not; a cell expected value data generating circuit for generating cell expected value data by selectively inverting the test expected value data in accordance with a position, in the memory array, of the selected memory cell; a modifying circuit for modifying the cell expected value data in accordance with a failure mode instruction signal for designating a failure mode to be detected; and a cell level determining circuit for generating a cell level determination result signal indicating whether the selected memory cell is failure or not in accordance with an output signal of the modifying circuit and an output signal of the determining circuit.
A test circuit device according to a third aspect of the invention includes: a reading circuit for reading data from a selected address in a memory array having a plurality of memory cells; an expected value register for storing an expected value of read data from the selected address in the memory array; and a determining circuit for determining whether or not a failure occurs in the memory cell at the selected address in accordance with output data of the reading circuit, data stored in the expected value register, the selected address, and a failure mode instruction signal for designating that a failure to be detected is a change from high-level data to low-level data of memory cell data or a change from the low-level data to the high-level data of the memory cell data and outputting a signal indicative of a result of the determination.
By modifying test expected value data in accordance with a selected address and the failure mode instruction signal, whether there is the possibility that a failure occurs in the memory cell in the selected address or not can be determined. By determining whether test data read from the selected address coincides with the test expected value data or not in accordance with the result of determination, the data stored in the memory cell is good or not with respect to the expected value can be determined in accordance with the position of the selected memory cell in the memory array. Thus, a failure at the memory cell level can be detected. Particularly, by instructing a failure mode to be detected by the failure mode instruction signal, the failure to be detected can be set to either an xe2x80x9cHLxe2x80x9d failure or xe2x80x9cLHxe2x80x9d failure. Whether the failure occurs in storage data in a memory cell or not can be determined according to the failure mode by scrambling the test expected value data in accordance with the selected address. For example, when the failure mode instruction signal designates detection of the HL failure, if the expected value of the data stored in the memory cell is L-level data, such an HL failure does not occur. Consequently, the data is eliminated from a target for detecting a failure. By detecting whether data coincides with the expected value data or not when data stored in the memory cell is at the H level, the HL failure can be detected. By selectively validating the operation of determining whether test data coincides with the test expected value data or not in accordance with the failure mode instruction signal, the HL failure and LH failure of the data stored in the memory cell can be detected. Thus, a failure can be detected at the memory cell level, and the mode in the event of the failure can be also detected, so that the analysis of a failure is facilitated.
By providing the test circuit device in a semiconductor memory device, the determining operation is performed inside the semiconductor memory device. In an external tester, by simply monitoring a failure mode to be detected and an address, without considering a test pattern and the physical position of a memory cell in a memory array, a distribution of HL failures and LH failures at the memory cell level can be detected, and the cause of a failure can be easily specified.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.